1. Field of the Invention
The present invention generally relates to generating and checking physical design data and, more particularly, a technique of nested image processing of physical design data to remove overlap in the data. The invention has particular application in the manufacture of semiconductor devices.
2. Description of the Prior Art
Integrated circuit (IC) shapes may be patterned on a semiconductor wafer by direct writing electron beam (E-beam) lithography. The intended pattern may be written directly onto the wafer by first exposing a thin layer of radiation sensitive material (resist) on the wafer with a beam of electrons. Alternatively, a thin layer of photoresist on the semiconductor wafer is exposed optically, using a mask made with an E-beam tool. Whether the pattern is directly written with an E-beam or indirectly written with a mask made with an E-beam, the E-beam tool remains the same.
Transferring computer designed patterns of very small geometric shapes that constitute the integrated circuit design to a physical image on a resist or a photoresist can be both expensive and time consuming. Most of the expense associated with transforming the shapes is computer operating cost, which is also generally time dependent. Therefore reducing computer operating time will reduce the expense associated with E-beam lithography.
The complete processing of the physical design data into numerical control (N/C) data can include the functions of Union, Fill (also known as Fracturing), Graysplicing and Proximity Correction.
Union is the process of removing overlap using the edges of the shapes as opposed to using shapes themselves. Overlap left in data sent to an electron beam (E-Beam) lithography tool can cause blooming (growing) of the resultant shapes in the resist. A variable shape electron beam tool, as opposed to a bit-mapped fixed shape electron beam tool, needs the overlap removed in its input data.
The Unioned edges or overlapped removed shapes are then sent to the Fill or Fracturing function. This function converts the input shapes into a set of shapes that the target tool can process. Often, the input shapes consist of rectangles, lines (or paths), polygons, alphanumerics and circles. The set of shapes that the electron beam tools can process is sometimes limited to rectangles and triangles. Some electron beam tools can handle trapezoids and parallelograms. The large set of shapes must be converted to the smaller, more restrictive, set of shapes for output.
A positive Fill involves converting the shapes as input into the set of tool-supported shapes. A negative Fill, or simply Negation, involves converting not the shapes, but the shapes' backgrounds into tool-supported shapes. A design that has a small data volume output in a positive image very likely will have a large data volume in the negative image and, therefore, a large processing time.
Graysplicing is the process of guaranteeing continuity between the subsets of the design that a tool can address at a given time. In some tools, these areas are called Fields and Subfields. Graysplicing involves "stitching" between fields and subfields that are not processed contiguously.
Proximity Correction is the process where each shape's properties are modified based on the influence of neighboring shapes. There are two main proximity correction techniques. One involves changing the shape's exposure time (dose), and the other involves moving the shape's edges. Either method needs information from neighboring shapes over a certain range or radius. Shapes significantly farther away than this range do not need to be figured into the calculations.
If all of these functions are performed unnested (that is, the data hierarchy is flattened), the processing time can be prohibitive.
As stated above, one of the steps involved in the transformation of the geometric shapes which comprise the IC design is overlap removal or Union. Overlap removal is necessary to prevent "blooming" when using E-beam lithography tools. Overlap removal is typically performed on a shape to shape basis. The shapes to be processed are unnested and checked. Alternative procedures are scanline union techniques. Scanline union (of edges) techniques are faster than shape to shape checks, but both techniques are processing time costly. In both of these methods, the pertinent shapes are unnested within a specified area.
U.S. Pat. No. 5,294,800 to Chung et al. describes nested cell processing for E-beam lithography data preparation. These nested cells are either ones that started out completely unintruded in the design data or are combinations of cells where the combination is unintruded. The latter kind of cell is actually partially unnested.
Design Rule Checking (DRC) is another area that involves examining the physical design. DRC includes verifying that one level of shapes of a semiconductor design are properly "covered" by another. Another area involves verifying that there is a complete path or circuit from one point in the design to another. Nested processing can be valuable for DRC also.
To process as much data nested as possible, one needs either to start out with highly nested data or some method to create nested data.